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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
NO OPERATION Command
Figure 81: Simplified Bus Interface State Diagram
Power
applied
Power-on
RE
SE
T
DPDX
Deep
power-down
Automatic sequence
Command sequence
Resetting
MR reading
MRR
Resetting
Self
refreshing
DPD
PD
PD
X
Resetting
power-down
Idle
MR reading
MRR
Idle 1
REF
Refreshing
MR writing
ACT
Idle
power-down
Active
power-down
Active
MR reading
PR
MR
PD
PD
X
R
BST
Active
BST
W
R
RD
PR = PRECHARGE
PRA = PRECHARGE ALL
ACT = ACTIVATE
WR(A) = WRITE (with auto precharge)
RD(A) = READ (with auto precharge)
BST = BURST TERMINATE
RESET = RESET is achieved through
MRW command
MRW = MODE REGISTER WRITE
MRR = MODE REGISTER READ
PD = enter power-down
PDX = exit power-down
SREF = enter self refresh
SREFX = exit self refresh
DPD = enter deep power-down
DPDX = exit deep power-down
REF = REFRESH
WR
Writing
WRA
Writing
with
auto precharge
PR, PRA
Precharging
RD
Reading
RDA
Reading
with
auto precharge
Note:
1. All banks are precharged in the idle state.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
104
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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